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?2008 silicon storage technology, inc. s71152-12-000 9/08 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. mtp is a trademark of silicon storage technology, inc. these specifications are subject to change without notice. data sheet 512 kbit / 1 mbit / 2 mbit (x8) many-time programmable flash sst27sf512 / sst27sf010 / sst27sf020 features: ? organized as 64k x8 / 128k x8 / 256k x8 ? 4.5-5.5v read operation ? superior reliability ? endurance: at least 1000 cycles ? greater than 100 years data retention ? low power consumption ? active current: 20 ma (typical) ? standby current: 10 a (typical) ? fast read access time ? 70 ns ? fast byte-program operation ? byte-program time: 20 s (typical) ? chip program time: 1.4 seconds (typical) for sst27sf512 2.8 seconds (typical) for sst27sf010 5.6 seconds (typical) for sst27sf020 ? electrical erase using programmer ? does not require uv source ? chip-erase time: 100 ms (typical) ? ttl i/o compatibility ? jedec standard byte-wide eprom pinouts ? packages available ? 32-lead plcc ? 32-lead tsop (8mm x 14mm) ? 32-pin pdip for sst27sf010/020 ? all non-pb (lead-free) devices are rohs compliant product description the sst27sf512/010/020 are a 64k x8 / 128k x8 / 256k x8 cmos, many-time programmable (mtp) low cost flash, manufactured with sst?s proprietary, high perfor- mance superflash technology. the split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. these mtp devices can be electrically erased and pro- grammed at least 1000 times using an external program- mer with a 12v power supply. they have to be erased prior to programming. these devices conform to jedec stan- dard pinouts for byte-wide memories. featuring high-performance byte-program, the sst27sf512/010/020 provide a byte-program time of 20 s. designed, manufactured, and tested for a wide spec- trum of applications, these devices are offered with an endurance of at least 1000 cycles. data retention is rated at greater than 100 years. the sst27sf512/010/020 are suited for applications that require infrequent writes and low power nonvolatile stor- age. these devices will improve flexibility, efficiency, and performance while matching the low cost in nonvolatile applications that currently use uv-eproms, otps, and mask roms. to meet surface mount and conventional through hole requirements, the sst27sf512 are offered in 32-lead plcc, 32-lead tsop, and 28-pin pdip packages. the sst27sf010/020 are offered in 32-pin pdip, 32-lead plcc, and 32-lead tsop packages. see figures 3, 4, and 5 for pin assignments. device operation the sst27sf512/010/020 are a low cost flash solution that can be used to replace existing uv-eprom, otp, and mask rom sockets. these devices are functionally (read and program) and pin compatible with industry standard eprom products. in addition to eprom func- tionality, these devices also support electrical erase operation via an external programmer. they do not require a uv source to erase, and therefore the pack- ages do not have a window. read the read operation of the sst27sf512/010/020 is con- trolled by ce# and oe#. both ce# and oe# have to be low for the system to obtain data from the outputs. once the address is stable, the address access time is equal to the delay from ce# to output (t ce ). data is available at the out- put after a delay of t oe from the falling edge of oe#, assuming that ce# pin has been low and the addresses have been stable for at least t ce -t oe. when the ce# pin is high, the chip is deselected and a typical standby current of 10 a is consumed. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either ce# or oe# is high. sst27sf512 / 010 / 0205.0v-read 512kb / 1mb / 2mb (x8) mtp flash memories
2 data sheet 512 kbit / 1 mbit / 2 mbit many-time programmable flash sst27sf512 / sst27sf010 / sst27sf020 ?2008 silicon storage technology, inc. s71152-12-000 9/08 byte-program operation the sst27sf512/010/020 are programmed by using an external programmer. the programming mode for sst27sf010/020 is activated by asserting 11.4-12v on v pp pin, v dd = 4.5-5.5v, v il on ce# pin, and v ih on oe# pin. the programming mode for sst27sf512 is activated by asserting 11.4-12v on oe#/v pp pin, v dd = 4.5-5.5v, and v il on ce# pin. these devices are programmed byte- by-byte with the desired data at the desired address using a single pulse (ce# pin low for sst27sf512 and pgm# pin low for sst27sf010/020) of 20 s. using the mtp pro- gramming algorithm, the byte-programming process con- tinues byte-by-byte until the entire chip has been programmed. chip-erase operation the only way to change a data from a ?0? to ?1? is by electri- cal erase that changes every bit in the device to ?1?. unlike traditional eproms, which use uv light to do the chip- erase, the sst27sf512/010/020 uses an electrical chip- erase operation. this saves a significant amount of time (about 30 minutes for each erase operation). the entire chip can be erased in a single pulse of 100 ms (ce# pin low for sst27sf512 and pgm# pin for sst27sf010/ 020). in order to activate the erase mode for sst27sf010/ 020, the 11.4-12v is applied to v pp and a 9 pins, v dd = 4.5- 5.5v, v il on ce# pin, and v ih on oe# pin. in order to acti- vate erase mode for sst27sf512, the 11.4-12v is applied to oe#/v pp and a 9 pins, v dd = 4.5-5.5v, and v il on ce# pin. all other address and data pins are ?don?t care?. the falling edge of ce# (pgm# for sst27sf010/020) will start the chip-erase operation. once the chip has been erased, all bytes must be verified for ffh. refer to figures 13 and 14 for the flowcharts. product identification mode the product identification mode identifies the devices as the sst27sf512, sst27sf010 and sst27sf020 and manufacturer as sst. this mode may be accessed by the hardware method. to activate this mode for sst27sf010/ 020, the programming equipment must force v h (11.4-12v) on address a 9 with v pp pin at v dd (4.5-5.5v) or v ss . to activate this mode for sst27sf512, the programming equipment must force v h (11.4-12v) on address a 9 with oe#/v pp pin at v il . two identifier bytes may then be sequenced from the device outputs by toggling address line a 0 . for details, see tables 3 and 4 for hardware operation. table 1: product identification address data manufacturer?s id 0000h bfh device id sst27sf512 0001h a4h sst27sf010 0001h a5h sst27sf020 0001h a6h t1.2 1152
data sheet 512 kbit / 1 mbit / 2 mbit many-time programmable flash sst27sf512 / sst27 sf010 / sst27sf020 3 ?2008 silicon storage technology, inc. s71152-12-000 9/08 figure 1: functional block diagram - sst27sf512 figure 2: functional block diagram - sst27sf010/020 y-decoder i/o buffers 1152 b2.1 address buffer x-decoder dq 7 - dq 0 a 15 - a 0 a 9 oe#/v pp ce# superflash memory control logic y-decoder i/o buffers 1152 b3.2 address buffer x-decoder dq 7 - dq 0 a ms - a 0 a 9 oe# ce# superflash memory control logic pgm# v pp a ms = a 17 for sst27sf020, a 16 for sst27sf010
4 data sheet 512 kbit / 1 mbit / 2 mbit many-time programmable flash sst27sf512 / sst27sf010 / sst27sf020 ?2008 silicon storage technology, inc. s71152-12-000 9/08 figure 3: pin assignments for 32-lead plcc figure 4: pin assignments for 32-lead tsop (8mm x 14mm) 1152 32-plcc p1.5 sst27sf512 sst27sf010/020 sst27sf010/020 sst27sf512 sst27sf512 sst27sf512 sst27sf010/020 sst27sf010 sst27sf020 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 a6 a5 a4 a3 a2 a1 a0 nc dq0 a7 a6 a5 a4 a3 a2 a1 a0 dq0 a8 a9 a11 nc oe#/v pp a10 ce# dq7 dq6 a14 a13 a8 a9 a11 oe# a10 ce# dq7 4 3 2 1 32 31 30 a7 a12 a15 nc v dd a14 a13 a12 a15 a16 v pp v dd pgm# nc a12 a15 a16 v pp v dd pgm# a17 32-lead plcc top view 14 15 16 17 18 19 20 dq1 dq2 v ss nc dq3 dq4 dq5 dq1 dq2 v ss dq3 dq4 dq5 dq6 1152 32-tsop p2.3 a11 a9 a8 a13 a14 nc nc v dd nc nc a15 a12 a7 a6 a5 a4 nc pgm# v pp a16 a17 pgm# v pp a16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 oe#/v pp a10 ce# dq7 dq6 dq5 dq4 dq3 v ss dq2 dq1 dq0 a0 a1 a2 a3 oe# oe# 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 standard pinout top view die up sst27sf512 sst27sf010 sst27sf020 sst27sf512 sst27sf020 sst27sf010
data sheet 512 kbit / 1 mbit / 2 mbit many-time programmable flash sst27sf512 / sst27 sf010 / sst27sf020 5 ?2008 silicon storage technology, inc. s71152-12-000 9/08 figure 5: pin assignments for 28-pin and 32-pin pdip table 2: pin description symbol pin name functions a ms 1 -a 0 1. a ms = most significant address a ms = a 15 for sst27sf512, a 16 for sst27sf010, and a 17 for sst27sf020 address inputs to provide memory addresses dq 7 -dq 0 data input/output to ou tput data during read cycles and re ceive input data during program cycles the outputs are in tri-state when oe# or ce# is high. ce# chip enable to activate the device when ce# is low oe# output enable for sst27sf010/020, to gate th e data output buffers during read operation oe#/v pp output enable/v pp for sst27sf512, to gate the data output buff ers during read operation and high voltage pin during chip-erase and programming operation v pp power supply for program or erase for sst27sf010/020, high voltage pin during chip-erase and programming operation 11.4-12v v dd power supply to provide 5.0v supply (4.5-5.5v) v ss ground nc no connection unconnected pins. t2.4 1152 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-pin pdip top view v pp a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 v ss v pp a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 v ss 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v dd pgm# nc a14 a13 a8 a9 a11 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 v dd pgm# a17 a14 a13 a8 a9 a11 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 1152 32-pdip p4.2 sst27sf010 sst27sf010 sst27sf020 sst27sf020 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28-pin pdip to p v i e w a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 v ss 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v dd a14 a13 a8 a9 a11 oe#/v pp a10 ce# dq7 dq6 dq5 dq4 dq3 1152 28-pdip p3.2 sst27sf512 sst27sf512
6 data sheet 512 kbit / 1 mbit / 2 mbit many-time programmable flash sst27sf512 / sst27sf010 / sst27sf020 ?2008 silicon storage technology, inc. s71152-12-000 9/08 note: v pph = 11.4-12v, v h = 11.4-12v note: v pph = 11.4-12v, v h = 11.4-12v table 3: operation modes selection for sst27sf512 mode ce# oe#/v pp a 9 dq address read v il v il a in d out a in output disable v il v ih x 1 high z x program v il v pph a in d in a in standby v ih x x high z x chip-erase v il v pph v h high z x program/erase inhibit v ih v pph x high z x product identification v il v il v h manufacturer?s id (bfh) device id (a4h) a 15 -a 1 =v il , a 0 =v il a 15 -a 1 =v il , a 0 =v ih t3.2 1152 1. x can be v il or v ih, but no other value. table 4: operation modes selection for sst27sf010/020 mode ce# oe# pgm# a 9 v pp dq address read v il v il x 1 1. x can be v il or v ih, but no other value. a in v dd or v ss d out a in output disable v il v ih xxv dd or v ss high z a in program v il v ih v il a in v pph d in a in standby v ih xxxv dd or v ss high z x chip-erase v il v ih v il v h v pph high z x program/erase inhibit v ih xxxv pph high z x product identification v il v il xv h v dd or v ss manufacturer?s id (bfh) device id 2 2. device id = a5h for sst27sf010 and a6h for sst27sf020 a ms 3 - a 1 =v il , a 0 =v il a ms 3 - a 1 =v il , a 0 =v ih 3. a ms = most significant address a ms = a 16 for sst27sf010 and a 17 for sst27sf020 t4.2 1152
data sheet 512 kbit / 1 mbit / 2 mbit many-time programmable flash sst27sf512 / sst27 sf010 / sst27sf020 7 ?2008 silicon storage technology, inc. s71152-12-000 9/08 absolute maximum stress ratings (applied conditions greater than t hose listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater t han those defined in the operational sections of this data sheet is not implied. exposu re to absolute maximum stress rating co nditions may affect device reliability.) temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0. 5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0v to v dd +2.0v voltage on a 9 and v pp pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 14.0v package power dissipation capability (t a = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w through hole lead soldering temperature (10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300c surface mount solder reflow temperature 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c for 10 seconds output short circuit current 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 m a 1. excluding certain with-pb 32-plcc units, all packages are 260 c capable in both non-pb and with-pb solder versions. certain with-pb 32-plcc package types are capable of 240 c for 10 seconds; please consult the factory for the latest information. 2. outputs shorted for no more than one second. no more than one output shorted at a time. o perating r ange range ambient temp v dd v pp commercial 0c to +70c 4.5-5.5v 11.4-12v ac c onditions of t est input rise/fall time . . . . . . . . . . . 10 ns output load . . . . . . . . . . . . . . . . . c l = 30 pf for 70 ns see figures 11 and 12 table 5: read mode dc operating characteristics for sst27sf512/010/020 v dd = 4.5-5.5v, v pp =v dd or v ss (t a = 0c to +70c (commercial)) symbol parameter limits test conditions min max units i dd v dd read current address input=v ilt /v iht at f=1/t rc min v dd =v dd max 30 ma ce#=oe#=v il , all i/os open i ppr v pp read current address input=v ilt /v iht at f=1/t rc min v dd =v dd max, v pp =v dd 100 a ce#=oe#=v il , all i/os open i sb1 standby v dd current (ttl input) 3mace#=v ih , v dd =v dd max i sb2 standby v dd current (cmos input) 100 a ce#=v dd -0.3 v dd =v dd max i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 10 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ih input high voltage 2.0 v dd +0.5 v v dd =v dd max v ol output low voltage 0.2 v i ol =2.1 ma, v dd =v dd min v oh output high voltage 2.4 v i oh =-400 a, v dd =v dd min i h supervoltage current for a 9 200 a ce#=oe#=v il , a 9 =v h max t5.6 1152
8 data sheet 512 kbit / 1 mbit / 2 mbit many-time programmable flash sst27sf512 / sst27sf010 / sst27sf020 ?2008 silicon storage technology, inc. s71152-12-000 9/08 table 6: program/erase dc operating characteristics for sst27sf512 v dd =4.5-5.5v, v pp =v pph (t a =25c5c) symbol parameter limits test conditions min max units i dd v dd erase or program current 30 ma ce#=v il, oe#/v pp =11.4-12v, v dd =v dd max i pp v pp erase or program current 3 ma ce#=v il, oe#/v pp =11.4-12v, v dd =v dd max i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 10 a v out =gnd to v dd , v dd =v dd max v h supervoltage for a 9 11.4 12 v ce#=oe#/v pp =v il, i h supervoltage current for a 9 200 a ce#=oe#/v pp =v il, a 9 =v h max v pph high voltage for oe#/v pp pin 11.4 12 v t6.5 1152 table 7: program/erase dc operating characteristics for sst27sf010/020 v dd =4.5-5.5v, v pp =v pph (t a =25c5c) symbol parameter limits test conditions min max units i dd v dd erase or program current 30 ma ce#=pgm#=v il, oe#=v ih , v pp =11.4-12v, v dd =v dd max i pp v pp erase or program current 3 ma ce#=pgm#=v il, oe#=v ih , v pp =11.4-12v, v dd =v dd max i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 10 a v out =gnd to v dd , v dd =v dd max v h supervoltage for a 9 11.4 12 v ce#=oe#=v il, i h supervoltage current for a 9 200 a ce#=oe#=v il, a 9 =v h max v pph high voltage for v pp pin 11.4 12 v t7.5 1152 table 8: recommended system power-up timings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. power-up to read operation 100 s t pu-write 1 power-up to write operation 100 s t8.1 1152 table 9: capacitance (t a = 25c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. i/o pin capacitance v i/o = 0v 12 pf c in 1 input capacitance v in = 0v 6 pf t9.0 1152 table 10: reliability characteristics symbol parameter minimum specification units test method n end 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. endurance 1000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 t10.3 1152
data sheet 512 kbit / 1 mbit / 2 mbit many-time programmable flash sst27sf512 / sst27 sf010 / sst27sf020 9 ?2008 silicon storage technology, inc. s71152-12-000 9/08 ac characteristics table 11: read cycle timing parameters v dd = 4.5-5.5v (t a = 0c to +70c (commercial)) symbol parameter min max units t rc read cycle time 70 ns t ce chip enable access time 70 ns t aa address access time 70 ns t oe output enable access time 35 ns t clz 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. ce# low to active output 0 ns t olz 1 oe# low to active output 0 ns t chz 1 ce# high to high-z output 25 ns t ohz 1 oe# high to high-z output 25 ns t oh 1 output hold from address change 0 ns t11.3 1152 table 12: program/erase cycle timi ng parameters for sst27sf512 symbol parameter min max units t as address setup time 1 s t ah address hold time 1 s t prt oe#/v pp pulse rise time 50 ns t vps oe#/v pp setup time 1 s t vph oe#/v pp hold time 1 s t pw ce# program pulse width 20 30 s t ew ce# erase pulse width 100 500 ms t ds data setup time 1 s t dh data hold time 1 s t vr oe#/v pp and a 9 recovery time 1 s t art a 9 rise time to 12v during erase 50 ns t a9s a 9 setup time during erase 1 s t a9h a 9 hold time during erase 1 s t12.0 1152
10 data sheet 512 kbit / 1 mbit / 2 mbit many-time programmable flash sst27sf512 / sst27sf010 / sst27sf020 ?2008 silicon storage technology, inc. s71152-12-000 9/08 table 13: program/erase cycle timing parameters for sst27sf010/020 symbol parameter min max units t ces ce# setup time 1 s t ceh ce# hold time 1 s t as address setup time 1 s t ah address hold time 1 s t prt v pp pulse rise time 50 ns t vps v pp setup time 1 s t vph v pp hold time 1 s t pw pgm# program pulse width 20 30 s t ew pgm# erase pulse width 100 500 ms t ds data setup time 1 s t dh data hold time 1 s t vr a 9 recovery time for erase 1 s t art a 9 rise time to 12v during erase 50 ns t a9s a 9 setup time during erase 1 s t a9h a 9 hold time during erase 1 s t13.0 1152
data sheet 512 kbit / 1 mbit / 2 mbit many-time programmable flash sst27sf512 / sst27 sf010 / sst27sf020 11 ?2008 silicon storage technology, inc. s71152-12-000 9/08 figure 6: read cycle timing diagram for sst27sf512/010/020 figure 7: chip-erase timi ng diagram for sst27sf512 1152 f03.0 data valid data valid t clz t olz t oh t rc t aa t oe t ohz t chz high-z dq 7-0 oe# ce# address t ce 1152 f04b.1 t a9h t vr t vph t vps t ew t prt v dd v ss oe#/v pp a 9 v pph v pph v ih v il dq 7-0 ce# address (except a 9 ) t a9s t art t vr
12 data sheet 512 kbit / 1 mbit / 2 mbit many-time programmable flash sst27sf512 / sst27sf010 / sst27sf020 ?2008 silicon storage technology, inc. s71152-12-000 9/08 figure 8: chip-erase timing diagram for sst27sf010/020 figure 9: byte-program timing diagram for sst27sf512 1152 f04c.1 t a9h t vr t vph t vps t ceh t prt v dd v ss v pp a 9 pgm# v pph v pph v ih v ih v il dq 7-0 oe# ce# address (except a 9 ) t a9s t art t ces t ew 1152 f05b.2 data valid address valid t ah t pw t dh t as t ds t vr v dd v pph high-z v ss t vph t prt t vps oe#/v pp dq 7-0 ce# address
data sheet 512 kbit / 1 mbit / 2 mbit many-time programmable flash sst27sf512 / sst27 sf010 / sst27sf020 13 ?2008 silicon storage technology, inc. s71152-12-000 9/08 figure 10: byte-program timing diagram for sst27sf010/020 1152 f05c.1 data valid address valid t ah t ceh t as t ds t dh v dd v pph high-z v ih v ss t ces t pw t vph t prt t vps v pp pgm# dq 7-0 oe# ce# address
14 data sheet 512 kbit / 1 mbit / 2 mbit many-time programmable flash sst27sf512 / sst27sf010 / sst27sf020 ?2008 silicon storage technology, inc. s71152-12-000 9/08 figure 11: ac input/output reference waveforms figure 12: a test load example 1152 f06.0 reference points output input v ht v lt v ht v lt v iht v ilt ac test inputs are driven at v iht (2.4 v) for a logic ?1? and v ilt (0.4 v) for a logic ?0?. measurement reference points for inputs and outputs are v ht (2.0 v) and v lt (0.8 v). input rise and fall times (10% ? 90%) are <10 ns. note: v ht - v high te s t v lt - v low te s t v iht - v input high test v ilt - v input low test 1152 f07.1 to tester to dut c l r l low r l high v dd
data sheet 512 kbit / 1 mbit / 2 mbit many-time programmable flash sst27sf512 / sst27 sf010 / sst27sf020 15 ?2008 silicon storage technology, inc. s71152-12-000 9/08 figure 13: chip-erase algorithm for sst27sf512 oe#/v pp = v pph oe#/v pp = v dd or v ss a 9 = v il or v ih wait for oe#/v pp and a 9 recovery time erase 100ms pulse (ce# = v il ) read device (ce# = oe# = v il ) device passed compare all bytes to ffh device failed 1152 f08b.2 start a 9 = v h no ye s
16 data sheet 512 kbit / 1 mbit / 2 mbit many-time programmable flash sst27sf512 / sst27sf010 / sst27sf020 ?2008 silicon storage technology, inc. s71152-12-000 9/08 figure 14: chip-erase algorithm for sst27sf010/020 start a 9 = v h , v pp = v pph a 9 = v il or v ih ce# = v il , oe# = v ih wait a 9 recovery time erase 100ms pulse (pgm# = v il ) read device device passed compare all bytes to ffh device failed 1152 f08c.1 pgm# = v ih no ye s
data sheet 512 kbit / 1 mbit / 2 mbit many-time programmable flash sst27sf512 / sst27 sf010 / sst27sf020 17 ?2008 silicon storage technology, inc. s71152-12-000 9/08 figure 15: byte-program algorithm for sst27sf512 start erase* oe#/v pp = v pph address = first location program 20s pulse (ce# = v il ) read device (ce# = oe# = v il ) device passed compare all bytes to original data increment address device failed 1152 f09b.2 last address? wait for oe#/v pp recoverytime oe#/v pp = v dd or v ss no no ye s ye s * see figure 13
18 data sheet 512 kbit / 1 mbit / 2 mbit many-time programmable flash sst27sf512 / sst27sf010 / sst27sf020 ?2008 silicon storage technology, inc. s71152-12-000 9/08 figure 16: byte-program algorithm for sst27sf010/020 start erase* v pp = v pph address = first location ce# = v il , oe# = v ih program 20s pulse (pgm# = v il ) read device device passed compare all bytes to original data increment address device failed 1152 f09c.1 last address? no no ye s ye s * see figure 14
data sheet 512 kbit / 1 mbit / 2 mbit many-time programmable flash sst27sf512 / sst27 sf010 / sst27sf020 19 ?2008 silicon storage technology, inc. s71152-12-000 9/08 product ordering information valid combinations for sst27sf512 SST27SF512-70-3C-NHE sst27sf512-70-3c-whe valid combinations for sst27sf010 sst27sf010-70-3c-nhe sst27sf010-70-3c-whe sst27sf010-70-3c-phe valid combinations for sst27sf020 sst27sf020-70-3c-nhe sst27sf020-70-3c-whe sst27sf020-70-3c-phe note: valid combinations are those products in mass producti on or will be in mass production. consult your sst sales representative to confirm availability of valid combinat ions and to determine availability of new combinations. environmental attribute e 1 = non-pb package modifier h = 32 pins or leads package type n = plcc p = pdip w = tsop (type 1, die up, 8mm x 14mm) temperature range c = commercial = 0c to +70c minimum endurance 3 = 1,000 cycles read access speed 70 = 70 ns device density - x8 organization 020 = 2 mbit 010 = 1 mbit 512 = 512 kbit voltage range s = 4.5-5.5v product series 27 = many-time programmable flash otp/eprom replacement with eprom pinout 1. environmental suffix ?e? denotes non-pb solder. sst non-pb solder devices are ?rohs compliant?. sst 27 sf 020 - 70 - 3c - nh e xx x x xxxx - xxx -x x -xx x x
20 data sheet 512 kbit / 1 mbit / 2 mbit many-time programmable flash sst27sf512 / sst27sf010 / sst27sf020 ?2008 silicon storage technology, inc. s71152-12-000 9/08 packaging diagrams figure 17: 32-lead plastic lead chip carrier (plcc) sst package code: nh .040 .030 .021 .013 .530 .490 .095 .075 .140 .125 .032 .026 .032 .026 .029 .023 .453 .447 .553 .547 .595 .585 .495 .485 .112 .106 .042 .048 .048 .042 .015 min. top view side view bottom view 1 232 .400 bsc 32-plcc-nh-3 note: 1. complies with jedec publication 95 ms-016 ae dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in inches (max/min). 3. dimensions do not include mold flash. maximum allowable mold flash is .008 inches. 4. coplanarity: 4 mils. .050 bsc .050 bsc optional pin #1 identifier .020 r. max. r. x 30
data sheet 512 kbit / 1 mbit / 2 mbit many-time programmable flash sst27sf512 / sst27 sf010 / sst27sf020 21 ?2008 silicon storage technology, inc. s71152-12-000 9/08 figure 18: 32-lead thin small outline package (tsop) 8mm x 14mm sst package code: wh 32-tsop-wh-7 note: 1. complies with jedec publication 95 mo-142 ba dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (max/min). 3. coplanarity: 0.1 mm 4. maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 1.20 max. 1mm pin # 1 identifier 12.50 12.30 14.20 13.80 0.70 0.50 8.10 7.90 0.27 0.17 0. 50 bsc 1.05 0.95 0.15 0.05 0.70 0.50 0- 5 detail
22 data sheet 512 kbit / 1 mbit / 2 mbit many-time programmable flash sst27sf512 / sst27sf010 / sst27sf020 ?2008 silicon storage technology, inc. s71152-12-000 9/08 figure 19: 32-pin plastic dual in-line pins (pdip) sst package code: ph 32-pdip-ph-3 pin #1 identifier c l 32 1 base plane seating plane note: 1. complies with jedec publication 95 mo-015 ap dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in inches (max/min). 3. dimensions do not include mold flash. maximum allowable mold flash is .010 inches. .200 .170 7 4 plcs. .600 bsc .100 bsc .150 .120 .022 .016 .065 .045 .080 .070 .050 .015 .075 .065 1.655 1.645 .012 .008 0 15 .625 .600 .550 .530
data sheet 512 kbit / 1 mbit / 2 mbit many-time programmable flash sst27sf512 / sst27 sf010 / sst27sf020 23 ?2008 silicon storage technology, inc. s71152-12-000 9/08 table 14: revision history number description date 02 ? 2002 data book feb 2002 03 ? document control release (sst internal): no technical changes apr 2002 04 ? corrected i h supervoltage current for a 9 from 100 a to 200 a in tables 5, 6, and 7 jul 2002 05 ? corrected the test conditions for i dd and i ppr in table 5 on page 7 sep 2003 06 ? corrected the max value for i pp from 1 ma to 3 ma (see tables 6 and 7) ? added mpns for non-pb packages (see page 19) nov 2003 07 ? 2004 data book ? corrected caption for figure 7 from ?read cycle? to ?chip-erase? nov 2003 08 ? removed 256 kbit parts - refer to eol product data sheet s71152(02) apr 2004 09 ? removed all 90 ns parts - refer to eol product data sheet s71152(03) ? added rohs compliance information on page 1 and in the ?product ordering infor- mation? on page 19 ? added the solder reflow temperature to the ?absolute maximum stress ratings? on page 7. mar 2005 10 ? removed obsolete latch-up parameter from table 10 on page 8 may 2005 11 ? corrected v pp voltage from 11.4-12.6v to 11.4-12v sep 2005 12 ? removed leaded parts. see s71152(04) ? end-of-life pg package and pg valid combination. see s71152(04) sep 2008 silicon storage technology, inc. ? 1171 sonora court ? sunnyvale, ca 94086 ? telephone 408-735-9110 ? fax 408-735-9036 www.superflash.com or www.sst.com

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